期刊文献+

大电流负载的片上LDO系统设计 被引量:3

Design of an On-Chip LDO System with Large Loading Current
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摘要 本文分析了传统大电流负载的LDO(Low-dropout Regulator)系统实现系统稳定性和瞬态响应提高的局限性,在此基础上,提出了一种片内集成的瞬态响应提高技术.此技术无需外挂电容和等效串联电阻(Equivalent SeriesResistor,ESR),即能使系统在全负载范围内保持稳定性和良好的纹波抑制能力.仿真结果表明,系统空载时,静态电流为64μA,且最大能提供800mA的负载电流,1KHz时的电源抑制比达到-60dB,当负载电流以800mA/5μs跳变时,最大下冲电压为400mV,上冲电压为536mV,恢复时间分别只需6.7μs和12.8μs,版图面积约为0.64mm2. This paper analyzes the stability and transient response enhancement limit of traditional LDO system and a Wan- sient response enhancement technique of on-chip I.DO system is presented.Based on the analysis, a transient response enhancement technique fully integrated on-chip is put forward. The proposed scheme not only results in stability within a wide range of load varia- tion, but also gets a good tipple rejection without off-chip capacitor and equivalent series resistor. It is demomtrated by simulation that the proposed circuit dissipates only 64μA of quiescent current with empty load and it is capable of delivering load current up to 800mA, the power supply rejection rote at 1KHz is about - 60d8. For a load step of 8(X)mA/SPs, the circuit has a maximum under- shoot of 400mV and a maximum overshoot of 536mV. The recovery time is only 6.7Ps and 12.8Ps respectively and the layout area is about 0.64ram2.
出处 《电子学报》 EI CAS CSCD 北大核心 2013年第7期1431-1435,共5页 Acta Electronica Sinica
基金 国家集成电路重大专项(No.2009ZX02023-003) 国家重点基础研究发展计划(No.2007CB935400 No.2010CB934300 No.2011CB309602 No.2011CB932800) 国家自然科学基金(No.60906004 No.60906003 No.61006087 No.61076121) 上海市科委资助项目(No.09QH1402600 No.1052nm07000) 电子薄膜与集成器件国家重点实验室开放基金(No.KFJJ201110)
关键词 瞬态响应 相位裕度 快速响应 低压差 大电流负载 transient response phase margin quick response low dropout large loading current
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参考文献9

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共引文献28

同被引文献22

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