摘要
Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in world- wide communication, the researchers still face the problems of how to deal with these resource constraint devices and en- hance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays （FPGAs）. The commonly used cryptographic algorithms for digital signature algorithm （DSA） are rivest-shamir-adleman （RSA） and elliptic curve cryptosystems （ECC） which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usu- ally, RSA is computed over GF（p）, and ECC is computed over GF（p） or GF（2P）. Moreover, embedded applications need advance encryption standard （AES） algorithms to pro- cess encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arith- metic unit for computing high radix RSA and ECC operations over GF（p） and GF（2P）, which also can be extended to support AES operations. A new high radix signed digital （SD） adder has been proposed to eliminate the carry propagations over GF（p）. The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8 MHz using approxi- mately 5.5k CLBs on Virtex-5 FPGA.
Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in world- wide communication, the researchers still face the problems of how to deal with these resource constraint devices and en- hance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays （FPGAs）. The commonly used cryptographic algorithms for digital signature algorithm （DSA） are rivest-shamir-adleman （RSA） and elliptic curve cryptosystems （ECC） which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usu- ally, RSA is computed over GF（p）, and ECC is computed over GF（p） or GF（2P）. Moreover, embedded applications need advance encryption standard （AES） algorithms to pro- cess encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arith- metic unit for computing high radix RSA and ECC operations over GF（p） and GF（2P）, which also can be extended to support AES operations. A new high radix signed digital （SD） adder has been proposed to eliminate the carry propagations over GF（p）. The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8 MHz using approxi- mately 5.5k CLBs on Virtex-5 FPGA.
基金
This work was supported by National Natural Science Foundation of China （Grant No. 61173036） and the Fundamental Research Funds for Chinese Central Universities.
