摘要
采用0.18μm CMOS工艺设计了一款6.25 GHz锁相环倍频器,该倍频器适用于12.5 Gbit/s半速率复接的串行器/解串器(SerDes)发射系统。该锁相环倍频器不仅为SerDes发射系统提供6.25 GHz的时钟,也为系统提供1.25 GHz占空比1∶4的时钟。设计中鉴频鉴相器采用真单相时钟(TSPC)触发器,电荷泵采用电流舵结构,压控振荡器采用三级双延时环路结构,20分频器中的高速五分频采用源极耦合场效应晶体管逻辑(SCFL)触发器、低速四分频采用TSPC触发器。电路芯片面积为0.492 mm×0.668 mm。测试结果显示,锁相环的锁定范围为4.78～6.6 GHz,在1.8 V电源电压下核心电路的功耗为67.5 mW。当锁相环工作在6.25 GHz时,10 MHz频偏处相位噪声为-98.5 dBc/Hz,峰峰抖动为15 ps,均方根(RMS)抖动为3.5 ps。
A 6.25 GHz phase-locked loop（PLL）frequency multiplier was designed in 0.18 μm CMOS process.The frequency multiplier was applied to the 12.5 Gbit/s half-rate serializer/deserializer（SerDes）transmitter system.The frequency multiplier provides 6.25 GHz clock and 1.25 GHz clock with 1∶ 4 duty cycle for the system.The true single phase clock（TSPC）flip-flop was applied to the phase frequency detector（PFD）.The current-steering structure was applied to the charge pump.The three-stage dual-path delay structure was applied to the voltage controlled oscillator（VCO）.And in the 20 divider,the source coupled fet logic（SCFL）flip-flop was applied to the high-speed divided-by-5 frequency divider while the TSPC flip-flop was applied to the low-speed divided-by-4 frequency divider.The area of the chip is 0.492 mm×0.668 mm.The tested results show that the PLL operates from 4.78 GHz to 6.6 GHz and its core circuit consumes 67.5 mW at 1.8 V supply voltage.When the PLL operating frequency is 6.25 GHz,the circuit achieves a phase noise of -98.5 dBc/Hz at 10 MHz offset and the output peak-to-peak jitter is 15 ps while the output RMS jitter is 3.5 ps.
出处
《半导体技术》
CAS
CSCD
北大核心
2012年第12期918-922,共5页
Semiconductor Technology
