摘要
文中提出了一种具有高抗干扰能力的对称结构改进型MRF逻辑,并由此采用混合设计策略实现了一个8位超前进位加法器.该加法器在Synopsys HSPICE模拟仿真平台上使用台积电的65nm低Κ电介质工艺器件模型进行了验证.电路仿真结果表明,在0.25V的工作电压下,该加法器的功耗达到了亚微瓦级.与先前的对应设计相比,晶体管数量减小44.3%,功耗降低了34.9%～38.8%.
A modified MRF logic with symmetrical structure is proposed in this paper, using which an 8-bit carry look-ahead adder is implemented based on a hybrid design methodology. The adder is verified using 65nm low-k TSMC technology on Synopsys HSPICE D-2010 platform. Simulations show that at 0. 25V supply voltage, the proposed adder consumes less than one microwatt per MHz. Compared with former design, the transistor count can be saved by 44. 3% and 34. 9%-38. 8% power consumption is reduced.
出处
《微电子学与计算机》
CSCD
北大核心
2012年第12期43-46,共4页
Microelectronics & Computer
