摘要
文章介绍了基于FPGA的高速数据采编器的硬件及逻辑上的研究和设计;硬件上,采用时钟管理芯片的一分三时钟以保证高速AD采样的一致性,LVDS传输加入电缆均衡器的设计,使数据传输距离延长到10m以上,数据信号更加稳定可靠;逻辑上,采用双系统时钟以提高设备的工作稳定性和可靠性,并对A/D采样数据进行重组,并发送给记录器进行存储,单路数据传输速度为59.4MByte/s;该数据记录器已通过温度循环试验、高温老练试验、电磁兼容试验、振动试验等,性能稳定,能够实现数据的高速可靠采样,完全满足工程实践的要求。
A project of high--speed data acquisition based on FPGA is introduced in this paper. It includes the design and research of hardware and logic. In the hardware, we use a three--clock of clock management chip in order to ensure high--speed AD sampling consis- tency. LVDS transmission joined cable equalizer design makes data transmission distance extended to more than 10m which makes the data signal more stable and reliahle~ In the logic, we use dual system clock to improve equipment stability and reliability and reorganize A / D sampled data which is sent to a recorder for storage. The single way transmission speed is 59. 4MByte / s. The data recorder has passed the temperature cycle test, high temperature aging test, electromagnetic compatibility testing, vibration testing and so on. Its performance is stable and it can achieve high speed sampling of data. So the data recorder can fully meet the requirements of Engineering practice.
出处
《计算机测量与控制》
CSCD
北大核心
2012年第11期3104-3106,共3页
Computer Measurement &Control
