摘要
数字三相锁相环中含有大量乘法运算和三角函数运算,占用大量的硬件逻辑资源。为此,提出一种数字三相锁相环的优化实现方案,利用乘法模块复用和CORDIC算法实现三角函数运算,并用Verilog HDL硬件描述语言对优化前后的算法进行了编码实现。仿真和实验结果表明,优化后的数字三相锁相环大大节省了FPGA的资源,并能快速、准确地锁定相位,具有良好的性能。
Since there are many multiplication operations and trigonometric function operations in the digital three-phase- locked loop, which will occupy too much hardware resource, an optimized scheme of the digital three-phase-locked loop is pro- posed in this paper. The multiplication module reuse and CORDIC algorithm are adopted in the scheme to realize the trigono- metric function operation. The digital three-phase-locked loops before and after optimization were decoded and implemented with Verilog HDL. The results of the simulation and the experiment verify the optimized digital three-phase-look loop can save the resource of FPGA, and lock the phase rapidly and accurately.
出处
《现代电子技术》
2012年第14期169-171,共3页
Modern Electronics Technique
