摘要
多比特子DAC的电容失配误差在流水线AIX:输出中引入非线性误差,不仅严重降低AEK、转换精腰.而且通常的校准技术无法对非线性误差进行校准.针对这种情况,本文提出了一种用于16位流水线ADC的多比特子DAC电容失配校准方法.该设计误差提取方案在流片后测试得到电容失配误差.进而计算不同输入情况下电容失配导致的MDAC输出误差,根据后级的误差补偿电路将误差转换为卡乏准码并存储在芯片中,对电容失配导致的流水级输出误差进行校准.仿真结果表明.卡《准后信噪失真比SINAD为93.34 dB.无杂散动态范围SFDR为117.86 dB,有效精度EN()B从12.63 bit提高到15.26 bit.
Capacitor mismatches in multi-bit sub-DAC will introduce non-linear errors in pipelined ADC output. Therefore, conversion resolution will be greatly deteriorated. But normal calibration technique cannot correct non- linear error. Based on this calibration requirement, a capacitor mismatch calibration for multi-bit sub-DAC in 16 bit pipelined ADC is presented in this paper. In this calibration, a post-production capacitor mismatch extraction method is designed. After mismatch errors are obtained, MDAC output errors of different inputs are calculated. According to these errors, calibration code are calculated and then be stored on chip to correct mismatch errors through compensation circuit. Simulation results show that after calibration, SINAI） is 93.34 dB, SFDR is 117.86 dB and ENOB increased from 12.63 bit to 15.26 bit.
出处
《微电子学与计算机》
CSCD
北大核心
2012年第6期172-176,179,共6页
Microelectronics & Computer
