期刊文献+

一种用于降低电容失配误差的电容选择配对技术

A Capacitor Paring Technique for Capacitor Mismatch Reduction
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摘要 对于开关电容模数转换器来说,电容失配是一种主要的非线性误差源.为了减少电容失配误差,本文提出了一种差分电容选择配对技术.该技术基于差分级电路的增益误差正比于差分采样电容和与差分反馈电容和之间的相对误差的原理,通过电容比较和电容交换等电路技术,对电路中的工作电容进行选择配对来减小增益误差.概率分析和Monte Carlo仿真表明,该技术可将模数转换器的线性指标提高0.6-bit以上.与其他电容失配校准技术相比,该技术具有校准电路简单、不影响模数转换速度、对工作环境变化不敏感等特点. Capacitor mismatching is a main source of error for switched-capacitor analog-to-digital converter.A differential capacitor pairing technique is presented to reduce capacitor mismatch error. By comparing the capacitance of capacitors and then accordingly exchanging the position of capacitors, the gain error of the stage, which is proportional to the relative error between the sum of differential sampling capacitors and the sum of differential feedback capacitors,is obviously reduced. Probability analysis and Monte Carlo simulation indicate that the linearity of the analog-to-digital converter can be improved by 0.6 bit. Compared with other capacitor mismatch calibration techniques,the proposed technique has characteristics such as simple calibration circuits, unweakened conversion speed, and insensitive to the operation environment.
出处 《电子学报》 EI CAS CSCD 北大核心 2008年第2期338-341,共4页 Acta Electronica Sinica
关键词 电容失配校准 流水线模数转换 电路技术 capacitor mismatch calibration pipelined A/D conversion circuit techniques
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参考文献8

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