摘要
本文采用Altera公司的FPGA器件Cyclone Ⅲ系列EP3C10作为核心器件构成了R-S(255,223)编码系统;利用Quartus Ⅱ 9.0作为硬件仿真平台,用硬件描述语言Verilog_HDL实现编程,并且通过JTAG接口与EP3C10连接。R-S(Reed-Solomon)码是一类纠错能力很强的特殊的非二进制BCH码,能应对随机性和突发性错误,广泛应用于各种通信系统中和保密系统中。R-S(255,223)码能够检测32字节长度和纠错16字节长度的连续数据错误信息。
This paper uses Altera company FPGA Cyclone III series EP3C10 devices as a core component of R-S （255223） coding system;Using Quartus II 9.0 as a hardware emulation platform, using hardware description language Verilog__HDL programming, and through the JTAG interface and EP3C10 conneetion.R-S （ Reed-Solomon ） code is a kind of special non binary BCH code which＇s error correction capability is very strong, can deal with random and burst error, widely used in all kinds of communication systems and security systems.R-S （255223） code is capable of detecting and correcting the length of 32 bytes 16 byte length of continuous data error information.
出处
《电子设计工程》
2012年第4期189-192,共4页
Electronic Design Engineering
