摘要
RS码是一种多进制分组循环码,检错和纠错能力强,尤其适合纠正突发错误,在通信系统中有着广泛的应用。本文所研究的RS(255,223)译码器采用修正的Euclid译码算法(MEA),介绍了一种基于FPGA的RS译码器的设计和硬件电路实现方案。按照自顶向下的设计流程,划分模块,详细论述了各子模块的设计过程。
RS code is a non-binary block cyclic code, and has strong capability in error-checking and error-correcting, especially in burst-error correcting, widely used in communication systems. RS(255,223) decoder proposed in this paper used Modified Euclidean Algorithm(MEA), introduced a design and hardware circuit solution of RS decoder on FPGA. According to top-to-down design flow, plotting blocks, this paper discussed the design procedure of each blocks in details.
出处
《微计算机信息》
北大核心
2005年第1期148-149,共2页
Control & Automation
