摘要
针对机载信息采集系统可靠性、数据管理高效性以及硬件成本的需求,介绍了基于硬件描述语言Verilog HDL设计的SDX总线与Wishbone总线接口转化的设计与实现,并通过Modelsim进行功能仿真,在QuartusⅡ软件平台上综合,最终在Altera公司的CycloneⅢ系列FPGA上调试。实验证明了设计的可行性。
Aiming at the requirement of reliability, high data management efficiency as well as hardware cost of the airborne information acquisition system, this article mainly introduces the interface conversion of Sdx-bus and Wishbone-bus. The implementation of the design is based on Verilog HDL Language. It is simulated on the Model- Sim software, synthesized on the Quartus platform and tested through FPGA from The Cyclone Ⅲ by Ahera company. The results show that the design is feasible.
出处
《电子科技》
2012年第1期65-68,共4页
Electronic Science and Technology
