摘要
为提高静电放电(ESD)防护器件的开启速度,减小被保护电路的损伤概率,在0.18μm CMOS混合信号工艺下,研究了结构参数、脉冲幅值对基于可控硅整流器(SCR)的ESD防护器件开启时间的影响。在基区渡越时间的基础上,加上了结电容的影响因素,完善了器件防护延迟模型,当注入脉冲电压值增大到700V时,模型最大误差<0.5ns,在分析快沿脉冲的防护时更符合实际情况。仿真结果表明:当阱间距取5.00μm,N+与P+间隔取0.50μm,SCR的开启时间可降为1ns。此外,在大幅值的脉冲注入下,由于结电容的充电速度加快,SCR的开启也更为迅速。实验结果验证了模型和仿真分析的准确性,在一定程度上增大阱间距的宽度,减小N+与P+的间隔可以缩短SCR的开启时间,为该类型防护器件的设计、参数优化提供了理论依据。
In order to accelerate the turn-on speed of electrostatic discharge（ESD） protection device,and to reduce the damage probability of vulnerable circuit,the effects of structural factors and pulse amplitude on silicon controlled rectifier（SCR） characteristics,particularly turn-on time,have been investigated in a 0.18 μm CMOS process.Both the base transit times and the junction capacitance charging time are considered in the delay model,and the error is always less than 0.5 ns,even the voltage of injecting pulse has increased to 700 V,which is more adaptive to study the fast rising edge ESD pulse.And the simulated results indicate that SCR can achieve a turn-on time as low as 1 ns,when the N＋ to P＋ spacing is 5.00 μm and well tap spacing is 0.50 μm.Furthermore,larger injecting pulse amplitude will lead to a less turn-on time,as a result of the decrease of base-emitter charging time.Simulation data and the experimental result agrees well with each other,and smaller N＋ to P＋ spacing and larger well tap spacing have the beneficial effect of lowering the SCR turn-on time.As a result,the model provides theoretical basis for the design and parametric optimization of ESD protection devices.
出处
《高电压技术》
EI
CAS
CSCD
北大核心
2011年第12期2891-2896,共6页
High Voltage Engineering
基金
国家自然科学基金(60971042)
国防科技重点实验室基金(9140C87020410JB3403)~~
关键词
可控硅整流器(SCR)
静电放电(ESD)防护器件
延迟特性
快沿脉冲
结构参数
结电容
silicon controlled rectifier（SCR）
electrostatic discharge（ESD） protection devices
delay characteristics
fast rising pulse
structural parameter
junction capacitance
