摘要
本文在综合多种数字信号系统设计方式优缺点的基础上,重点介绍用VHDL[Very High Speed Integrated Circuit(VHSIC)Hardware Description Language]语言在硬件芯片FPGA/CPLD上进行数字信号处理,设计移位相加硬件乘法器,实现快速乘法功能,并以Altera公司的ACEX1K系列产品作为硬件,将Max+plusⅡ软件作为开发工具,进行设计编码、功能仿真和硬件测试。
This paper is based on summarizing several kinds of advantage as well as disadvantage of system designs in digital signal process and it mainly introduces the digital signal process on the hardware chip FPGA/CPLD using VHDL[Very High Speed Integrated Circuit(VHSIC) Hardware Description Language],the realization of the high-speed multiplier,and Using the Max+plusⅡ software as the exploiting tool to design program,function simulate and hardware test with ACEX1K series the product of Altera company.
出处
《电子测量与仪器学报》
CSCD
2008年第S2期145-148,共4页
Journal of Electronic Measurement and Instrumentation
关键词
乘法器
硬件描述语言
数字信号处理
Multiplier Hardware Description Language(HDL) Digital Signal Process
