期刊文献+

FPGA测试配置完备性的分析评价方法 被引量:4

A Technique for FPGA Test Configuration Analysis and Evaluation
下载PDF
导出
摘要 测试配置开发是FPGA测试中的重要环节之一,为加快FPGA测试配置开发进程,提出一种基于配置词典的FPGA测试配置分析评价方法.首先建立FPGA基本可编程单元的配置词典,给出其完备测试需要的所有配置码;然后采用模板化的方法分析测试配置,计算测试配置对配置词典的覆盖率;最后根据计算的覆盖率评价测试配置的完备性.实验结果表明,文中方法能够正确地评价测试配置的完备程度,报告测试配置所有可测和不可测的FPGA资源;与故障仿真方法相比,该方法的时间复杂度从O(kpn2)减少到O(kn′),运行时间从数百小时缩短到几分钟,且运行时间独立于FPGA的阵列规模. Test configuration development is an essential step in FPGA test, to accelerate the development, a technique for FPGA test configuration analysis and evaluation based on configuration dictionary is presented in this paper. Firstly, the proposed method builds configuration dictionary of the basic programmable cells in FPGA, which contains all the configurations that the full test needs. Then the template method is used to analyze the test configuration and compute the coverage of the test configuration to the configuration dictionary. Experimental results show that the proposed method can perform exact evaluation to test configuration and report the detected and undetected FPGA resource of the test configuration. Compared with fault simulation method, it reduces time complexity from O(kpne) to O(kn') and is several orders of magnitude faster. Furthermore the operating time is independent of FPGA size.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2011年第10期1672-1679,共8页 Journal of Computer-Aided Design & Computer Graphics
基金 国家重大科学研究计划(2011CB933202)
关键词 FPGA 测试覆盖率 故障仿真 测试配置 FPGA test coverage fault simulation test configuration
  • 相关文献

参考文献12

  • 1杨海钢,孙嘉斌,王慰.FPGA器件设计技术发展综述[J].电子与信息学报,2010,32(3):714-727. 被引量:219
  • 2Hsu C L, Chen T H. Built in self-test design for fault detection and fault diagnosis in SRAM-based FPGA [J]. IEEE Transactions on Instrumentation and Measurement, 2009, 58(7): 2300-2315. 被引量:1
  • 3Dutton B F, Stroud C E. Built-in self test of configurable logic blocks in Virtex-5 FPGAs [C] //Proceedings of the 41st Southeastern Symposium on System Theory. Los Alamitos: IEEE Computer Society Press, 2009:230-234. 被引量:1
  • 4Tahoori M B, Mitra S. Application-independent testing of FPGA interconnects [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(11): 1774-1783. 被引量:1
  • 5Dutton B F, Stroud C E. Built-in self-test for programmable input/output tiles in Virtex-5 FPGAs [C] //Proceedings of the 41st Southeastern Symposium on System Theory. Los Alamitos: IEEE Computer Society Press, 2009:235-239. 被引量:1
  • 6Toutounchi S, Lai A. FPGA test and coverage [C] // Proceedings of International Test Conference. Los Alamitos: IEEE Computer Society Press, 2002:599-607. 被引量:1
  • 7Lu S K, Wu H C, Tsai Y C. Efficient fault simulation techniques and test configuration generation for embedded FPGAs [C] //Proceedings of the IEEE International Symposium on Micro-Nano Mechatronics and Human Science. Los Alamitos: IEEE Computer Society Press, 2003, 2: 864- 867. 被引量:1
  • 8Tahoori M B, Mitra S. Techniques and algorithms for fault grading of FPGA interconnect test configurations [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23(2): 261-272. 被引量:1
  • 9Tahoori M B, Mitra S, FPGA interconnect test the International Test Computer Society Press, Toutounchi S, et al. Fault grading configurations [C] //Proceedings of Conference. Los Alamitos:IEEE 2002, 608-612. 被引量:1
  • 10韩睦华,刘雷波,魏少军.基于模板的SoC结构自动划分方法[J].计算机辅助设计与图形学学报,2009,21(5):680-687. 被引量:2

二级参考文献126

  • 1吴强,边计年,薛宏熙.基于抽象体系结构模板的多路软硬件划分算法[J].计算机辅助设计与图形学学报,2004,16(11):1562-1567. 被引量:7
  • 2孙劼,童家榕.层次式布线资源FPGA连线开关的设计[J].微电子学,2005,35(4):404-408. 被引量:4
  • 3Veenstra K. Multiplexer structures for use in making controllable interconnections in integrated circuits: United States, 5486775 [P]. 1996-01-23. 被引量:1
  • 4Nazarian H A, Douglass S M, Graf W A, et al. Methods for maximizing routability in a programmable interconnect matrix having less than full connectability: United States, 6243664 B1 [P]. 2001-06-05. 被引量:1
  • 5Zhou C L, Wu Y L, Tang W C. Use augmented connection boxes to improve FPGA performance[C]//Proceedings of International Conference on Communications, Circuits and Systems, Guilin, 2006:2469-2473. 被引量:1
  • 6Fujiyoshi K, Kajitani Y, Niitsu H. Design of minimum and uniform bipartites for optimum connection blocks of FPGA [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997, 16(11) : 1377-1383. 被引量:1
  • 7Guo W M, Oruc A Y. Regular sparse crossbar concentrators [-J]. IEEETransactions on Computers, 1998, 47(3): 363- 368. 被引量:1
  • 8Altera Inc. Flex 10 K embedded programmable logic device family data sheet (V4.2)[OL]. [2008-03-08]. http,//www. altera, com. 被引量:1
  • 9Betz V, Rose J. Automatic generation of FPGA routing architectures from high-level descriptions [C] // Proceedings of the 8th International Symposium on Field Programmable Gate Array, Monterey, 2000:175-184. 被引量:1
  • 10Lemieux G G F. Efficient interconnection network components for programmable logic devices [D]. Toronto: University of Toronto, 2003. 被引量:1

共引文献220

同被引文献36

  • 1陈卫兵,陈键.一种RAM自检的新方法[J].工业控制计算机,2006,19(9):69-69. 被引量:6
  • 2李雪莲,李月香,袁涛.FPGA测试中故障屏蔽现象的分析和研究[J].测试技术学报,2007,21(6):557-561. 被引量:4
  • 3Hui Zhao. The Application of Boundary-Scan Technol-ogy to FPGA-Based Experiment System[J]. The NinthInternational Conference on Electronic Measurement In-struments, 2009(7):629-632. 被引量:1
  • 4Renavell M, el al. Testing the Interconnect of RAM-Based FPGA[J]. IEEE Design &- Test of computers.1998(5):45-50. 被引量:1
  • 5Toutounchi S, Lai A. FPGA test and coverage[C]//Los Alamitos. CA: IEEE Computer Society Press,2002(7):599-607. 被引量:1
  • 6Tahoori M B,Mitra S. Application-independent testingof FPGA interconnects [J]. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Sys-tems, 2005( 11) :1774. 被引量:1
  • 7Normand E. Single event upset at ground level[J]. IEEE Transactionson Nuclear Science Part 1, 1996, 43(6): 2742-2750. 被引量:1
  • 8Baumann R C. Radiation-induced soft errors in advanced semiconductortechnologies[J]. IEEE Transactions on Device andand Materials Reliability, 2005, 5(3): 305-316. 被引量:1
  • 9Carmichael C. Triple modular redundancy design techniquesfor Virtex FPGA’s [M]. San Jose : Xilinx, 2006. 被引量:1
  • 10Huang K H, Hu Y, Li X W. Reliability-oriented placement androuting algorithm for SRAM-based FPGAs[J]. IEEE Transactionson Very Large Scale Integration Systems, 2014, 22(2):256-269. 被引量:1

引证文献4

二级引证文献15

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部