摘要
提出了一种层次式布线资源FPGA连线开关的设计方法,采用迷宫算法,对连线开关的结构进行了分析。针对连线连接盒CB(connectionbox),提出了较为节省芯片面积的半连通结构;针对连线开关盒SB(switchbox),在给出连通度fs概念后,提出了使SB连通能力达到最大值的设计方法,并通过数学推导予以证明。应用这种设计方法,设计了一种fs=3的SB;成功地实现了采用这种结构的SB和半连通CB作为连线开关的FPGA芯片FDP100K。该芯片在电路布通率和芯片面积方面取得了较好的平衡结果。
A method to design connection switch for FPGA of the hierarchical interconnection resource is presented. Maze routing algorithm has been used to analyze the architecture of connection switch. A half connection architecture for CB is introduced, with which chip area can be reduced. The concept of connectivity fs is described, and the design method to maximize the connectivity of SB is proposed, which is then proved by mathematical deduction.Using this method, an SB with fs=3 is designed, and an FPGA chip using such SB and half connection CB has been implemented. This chip has made good balance between circuit routability and chip area.
出处
《微电子学》
CAS
CSCD
北大核心
2005年第4期404-408,共5页
Microelectronics
基金
国家自然科学基金资助项目(60076014)
教育部高等学校博士学科点科研基金资助项目(2000024623)
关键词
FPGA
互连资源
连接盒
开关盒
布通率
FPGA
Interconnection resource
Connection box
Switch box
Routability
