7Mukherjee Rajarshi, Memik Seda Ogrenci, Memik Gokhan. Peak temperature control and leakage reduction during binding in high level synthesis [ C ] //Proceedings of International Symposium on Low Power Electronics and Design, San Diego, 2005 : 251-256 被引量：1
8Wang Ling, Wen Dong-Xin, Yang Xiao-Zong, et al. Synthesis scheme for low power designs under timing constraints [J]. Chinese Journal of Semiconductors, 2005, 26(2) : 287-293 被引量：1
9SIA. International technology roadmap for semiconductors 2006 update [OL]. [2007-01-31] . http://www.itrs.net/Links/2006Update/FinalToPost/00_ExecSum2006 Update. pdf 被引量：1
10Srikantam V K, Ranganathan N, Srinivasan S. CREAM: combined register and module assignment with floorplanning for low power datapath synthesis [ C] //Proceedings of the 13th International Conference on VLSI Design, Calcutta, 2000:228 -233 被引量：1
