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高阶锁相环稳定性因子的定值分析 被引量:1

The Stability Factor Setting Value Analysis for PLL
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摘要 通过研究典型高阶电荷泵锁相环系统的相位传输模型及相位传输函数和相位误差传输函数,利用一元二次不等式方程的实数根判别式等常规数学工具,建立影响典型高阶系统稳定性的参数方程,推导出高阶锁相环路稳定性因子(二阶滤波比率m、系统衰减因子ζ)的取值方法,并计算出在保证环路相位裕度大于60°条件下参数值的范围(查找表),在同类环路的稳定性设计时可查阅参考。 The parameter equation of influencing the systematical stability was established by studying the phase transfer model,the phase transfer function and the error of transfer function of the typical higher-order charge pump phase-locked loop system and using the real root discriminant methods of unitary quadratic function inequality equation.The high-order phase-locked loop stability factor(second-order filter ration m and system attenuation factor ζ)were deduced by the generating ways.And the parameter value ranges(look-up table)were calculated in ensuring the margin of the loop phase under the conditions more than 60°.It has certain directive significance for the design of similar loop.The stability design of similar loop can be referred.
作者 李仲秋
出处 《电子器件》 CAS 2011年第3期337-340,共4页 Chinese Journal of Electron Devices
基金 湖南省教育厅资助科研项目(09C1058)
关键词 锁相环 稳定性 传输函数 衰减因子 参数方程 定值分析 PLL stability transfer function damping factor parameter equation constant value analysis
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  • 1周润德等译.数字集成电路,电子工业出版社,2004. 被引量:1
  • 2J.Maneatis and M.Horowitz,Precise delay generation using coupled oscillators,IEEE J.Solid-state Circuits,Vol.28,No 12,Dec.1993 pp1273-1282. 被引量:1
  • 3Roland E.Best,Phase-Locked Loops Design,Simulation,And Applications,McGraw-Hill,1999. 被引量:1
  • 4J.Maneatis,Low_Jitter and Process-Independent DLL and PLL Based on self-Biased Techniques ISSCC,1996. 被引量:1
  • 5John G.Maneatis and Mark A.Horowitz,Precise Delay Generation Using Coupled Oscillators,IEEE JSSC,Vol.28.No 12.Dec 1993. 被引量:1
  • 6Craninckx J and Steyaert M.A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors[J].IEEE J Solid-State Circuits,May 1997,32:736-744. 被引量:1
  • 7Niknejad.Analysis,Simulation,and Applications of Passive Devices on Conductive Substractes[D].PhD thesis,University of California at Berkeley,2000. 被引量:1
  • 8Maget J,Tiebout M,Kraus R,MOS Varactors With n-and p-Type Gates and Their Influence on an LC-VCO in Digital CMOS[J].IEEE J Solid-State Circuits,July 2000,38:1139-1147. 被引量:1
  • 9Andreani P,Mattisson S,On the Use of MOS Varactors in RF VCO's[J].IEEE J.Solid-State Circuits,June 2000,35:905-910. 被引量:1
  • 10Hung C and Kenneth K O,A packaged 1.1-GHz CMOS VCO with phase noise of 126 dBc/Hz at a 600-kHz offset[J].IEEE J.Solid-State Circuits,Jan.2000,35:100-103. 被引量:1

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