摘要
提出一种可配置的64位乘加器。根据计算模式的不同,该乘加器能够1次完成1个64×64、2个32×32、4个16×16和8个8×8的有/无符号乘加计算。在部分积(pp)产生电路中插入模式相关的选择器,并在最终树和最后的加法器中插入模式相关的进位消除电路,来实现乘加器的可配置。通过对部分积重新进行编排,避免了在部分积压缩树中插入进位消除电路。在部分积压缩树中,采用一种低功耗4∶2压缩器,有效降低了功耗和面积。最后,对乘加器的速度、面积和功耗等性能进行了分析。
A reconfigurable 64-bit multiply-accumulator（MAC） was presented.Depending on different computation mode,the MAC was capable of performing one 64×64,two 32×32,four 16×16 or eight 8×8 signed/unsigned multiply-accumulate operations.The MAC was ＂vectorized＂ by inserting mode-dependent selectors into partial product（pp） generation and inserting mode-dependent kills in carry chain of the final tree and final adder.In this work,insertion of kills into carry chain of the product reduction tree was avoided by relocating the partial product.Using low-power 4∶2 compressor in partial product tree,both power and area were reduced efficiently.Performances of the MAC,such as speed,power and area,were analyzed.
出处
《微电子学》
CAS
CSCD
北大核心
2011年第2期255-259,共5页
Microelectronics
关键词
乘加器
可配置乘加器
4∶2压缩器
Multiply-accumulator
Reconfigurable multiply-accumulator
4∶2 compressor
