摘要
综合的32位乘加器需采用5段流水线才能满足CPU的设计指标,但这样会造成与CPU指令流水线不匹配,带来了控制复杂化。为解决这个问题,采用互补传输门逻辑(CPL)设计了用于32位CPU的高速乘加器,使其流水线段数从原来的5段缩减为与CPU指令流水线相匹配的3段,简化了控制、降低了功耗、节省了面积。
To meet the specification of a CPU, a 5-stage pipeline structure is usually adopted for a synthesized multiplier accumulator, which, however, leads mismatch between MAC pipeline and instruction's pipeline, making the control logic more complex. A high-speed CPL-based multiplier accumulator circuit is presented in the paper. The circuit reduces the number of MAC pipeline stages from 5 to 3, which matches the instruction's pipeline, simplifying the control logic and cutting down both the power and chip area.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第6期670-674,共5页
Microelectronics
基金
国家自然科学基金资助项目(60276016
60476015)
清华大学校基础研究基金资助项目(JC2003059)
