摘要
DPA(Differential Power Analysis)攻击的强度取决于芯片电路功耗与所处理的数据之间的相关性以及攻击者对算法电路实现细节的了解程度.本文结合动态差分逻辑和可配置逻辑的特点,提出了一种具有抗DPA攻击能力的双端输出可配置逻辑(DRCL:Dual-Rail Configurable Logic).该逻辑一方面具有与数据取值无关的信号翻转率和信号翻转时刻,因而能够实现很好的功耗恒定特性;另一方面去除了电路结构与电路功能之间的相关性,从而可以阻止攻击者通过版图逆向分析的方法窃取算法电路实现细节.实验结果表明,DRCL比典型的抗DPA攻击逻辑WDDL(Wave Dynamic Differential Logic)具有更好的功耗恒定性,因而具有更强的DPA攻击防护性能.
The efficiency of Differential Power Analysis（DPA） depends on the correlation between power consumption and data value,as well as the attacker′s understanding of circuit details.To counteract DPA attack,this paper presents a novel logic,Dual-Rail Configurable Logic（DRCL）,which combines the characteristics of dynamic differential logic and configurable logic.The DRCL has constant power consumption which is independent of the data value.At the same time,the uniform structure of DRCL prevents attackers from revealing circuit details by layout reverse analysis.The experimental results show that the proposed logic DRCL has better power constant than the typical DPA resistant logic WDDL.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2011年第2期453-457,共5页
Acta Electronica Sinica
基金
国家自然科学基金(No.60970036)
国家863高技术研究发展计划(No.2009AA01Z124)
关键词
安全芯片
旁路攻击
功耗分析攻击
动态差分逻辑
可配置逻辑
security chip
side channel attack
differential power analysis
dynamic differential logic
configurable logic
