摘要
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法，并建成了相应的测试生成系统ＡＴＧＴＡ－１。该系统采用有限回溯测试模式产生方法生成测试码，采用ｎ（机器字长）个测试码并行的单故障传播方法模拟验证测试覆盖。测试生成与故障模拟为ｎ对１紧耦合集成方式。该系统运行１０个Ｂｅｎｃｈｍａｒｋ电路，取得了低测试长度、高故障覆盖、高效率的良好效果。
This paper presents a high speed test generation method specifically for very large scale combination circuit and full scan designed circuit.This method is used together with the finite backtracing test pattern generation method to generate test code,and then simulates to validate the fault covering by means of single fault propogating method with n(machine word) test code parallelised.The mode for test generation and fault simulation is n to 1 tight coupled integrating mode.With testing the method with 10 benchmark circuits,the result is good for low test pattern length,high fault coverage and high efficiency.
出处
《国防科技大学学报》
EI
CAS
CSCD
1999年第2期37-41,共5页
Journal of National University of Defense Technology
基金
国家自然科学基金
关键词
VLSI
组合电路
测试生成系统
ATGTA-1
full scan design,finite backtracing test pattern generation, n to 1 tight coupled integrating mode,test code parallelism,single fault propogation,very large scale combination circuit
