摘要
基于多项式除法提出一种单字节高速并行CRC算法,利用此单字节CRC校验码和任意多字节CRC校验码之间的逻辑关系,用单字节高速并行CRC算法可以实现任意字节长度数据的CRC校验码计算。基于FPGA器件以CRC-16编码为例,布线后仿真结果表明该算法在并行度为8-bit和16-bit时数据吞吐率分别可以达到1159.4Mbps和2253.5Mbps,与已有的查表法和其他并行CRC算法相比,该算法具有速度高、节省逻辑资源的特点。
The principle and implementation of a general and parallel CRC computing is proposed. Based on the polynomial-division, a parallel high-speed CRC computing for single byte is presented and furthermore, based on which the way for arbitrary bytes CRC computing is also given. The post-route simulation results for sigle-byte and dual-byte CRC computing based on FPGA component demonstrates that the data throughputs are as high as 1159.4 Mbps and 2253.5Mbps respectively. Compared with the Table-lookup algorithm and other parallel algorithms, the algorithm is high-speed and can save more hardware logic resources.
出处
《微计算机信息》
2010年第27期110-111,167,共3页
Control & Automation
关键词
并行CRC
检错
多项式除法
FPGA
parallel CRC
error check
polynomial-division
FPGA（Shanghai Institute of Micro-system and Information technology Chinese Academy Of Science
Shanghai 200050
China） （Graduate School of Chinese Academy of Science Beijing
100039
China）
