摘要
内置SRAM是单片集成TFT-LCD驱动控制芯片中的图像数据存储模块.针对内置SRAM的低功耗设计要求,采用HWD结构和动态逻辑的字线译码电路,实现了1.8MbSRAM的低功耗设计.电路采用0.18μm CMOS工艺实现,Hspice和Ultrasim仿真结果表明,与静态字线译码电路相比,功耗减小了20%;与DWL结构相比,功耗减小了16%;当访存时钟频率为31MHz时,SRAM存储单元的读写时间小于8ns,电源峰值功耗小于123mW,静态功耗为0.81mW.
The embedded SRAM is an important block for monolithic TFT-LCD driver IC used for storing image data. To meet the requirement of low-power, this paper presents a 1.8Mb HWD SRAM with dynamic word line decoder. Based on SMIC 0.18μm CMOS process, the designed SRAM is verified by Hspice and Ultrasim. The peak dynamic power dissipa- tion of dynamic word line decoder decreases by 2096 than that of static word line decoder. The peak dynamic power dissipation of designed SRAM decreases by 16% than that of DWL SRAM. The simulation results show that the reading and writing time are less than 8ns, dynamic peak power dissipation is less than 123roW and the static power dissipation is 0. 81mW at the operating frequency of 31MHz.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第9期172-175,180,共5页
Microelectronics & Computer
基金
陕西省重大科技创新项目(2007ZKC02-01)
