期刊文献+

SEU加固存储单元多节点翻转的准三维数值模拟 被引量:2

Quasi-Three-Dimensional Simulation of MNU in SEU Hardened Storage Cells
下载PDF
导出
摘要 为了深入了解SEU加固存储单元中多节点翻转的内部电荷收集及电压变化机制,采用准三维模拟工具MEDICI,对DIED加固单元进行器件/电路的混合模拟.结果表明,瞬时浮制节点和电荷的横向扩散是多节点翻转的关键原因.还研究其他加固单元多节点翻转的特点,并给出了避免多节点翻转的方法. We study the interplay of the charge collection and voltage change of multiple-node upset in SEU hardened cell,using the quasi-3D device/ circuit mixed-mode simulation in a DICE cell. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We also compare the MNU in other SEU hardened cells,and discuss the methods to avoid MNU.
出处 《微电子学与计算机》 CSCD 北大核心 2010年第5期99-102,共4页 Microelectronics & Computer
基金 国家核高基专项项目(2008ZX01019-001)
关键词 多节点翻转 电荷收集 准三维模拟 SEU multiple-node upset(MNU) charge collection quasi-3D simulation SEU
  • 相关文献

参考文献9

  • 1Rockett L. An SEU hardened CMOS data latch design[J ]. IEEE Trans. Nucl. Sci. , 1988, 35(6): 1682. 被引量:1
  • 2Velazco R, Bessot D. Two CMOS memory cells suitable for the design of SEU - tolerant VLSI circuits[J]. IEEE Trans. Nuel. Sci. , 1994, 41(6) : 2229. 被引量:1
  • 3Whitaker S, Canaris J, Liu K. SEU hardened memory cells for a CCSDS reed solomn eneoder[ J ]. IEEE Trans. Nucl. Sci., 1991,38(6) : 1471. 被引量:1
  • 4Wiseman D, Canaris J, Whitaker S. Design and testing of SEU/SEL immune memory and logic circuits in a commercial CMOS process[ C]//NSREC Workshop. New Mexico, 1993. 被引量:1
  • 5Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submieron CMOS technology [ J ]. IEEE Trans. Nucl. Sci. , 1996, 43(6) : 2874. 被引量:1
  • 6Castellani - Coulie K, Sagnes B, Saignd F. 3 - D device simulation[ C]//Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems. [ S. L. ], 2003. 被引量:1
  • 7Dxtd P E, Sexton F W, Winokur P S. Three- dimensional simulation of charge collection and multiple - bit upset in Si devices[J]. IEEE Trans. Nucl. Sci. , 1994, 41 (6) : 2005. 被引量:1
  • 8李玉红,赵元富,岳素格,梁国朕,林任.0.18μm工艺下单粒子加固锁存器的设计与仿真[J].微电子学与计算机,2007,24(12):66-69. 被引量:10
  • 9王亮,赵元富,岳素格.两个低开销抗单粒子翻转锁存器[J].微电子学与计算机,2007,24(12):221-224. 被引量:3

二级参考文献9

  • 1Dodd P E, Massengill L W. Basic mechanisms and modeling of single-event upset in digital microelectronics [J]. IEEE Trans. Nucl. Sci., 2003, 50(3): 583- 602 被引量:1
  • 2Robert C, Baumann. Radiation-induced soft errors in advanced semiconductor technologies [J]. IEEE Trans. Dev. and Mat., 2005, 5(3): 305-316 被引量:1
  • 3Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology [J]. IEEE Trans. Nucl. Sci., 1996, 43(6): 2874-2878 被引量:1
  • 4Michael Nicolaidis, Design for soft error mitigation [J]. IEEE Trans. Dev, and Mat., 2005, 5(3): 405-418 被引量:1
  • 5Mavis D G, Eaton P H. Soft error rate mitigation techniques for modern microcircuits [C]. in Proc. 40th Annu. Reliability Physics Symp., 2002:216-225 被引量:1
  • 6Gadlage M J, Schrimpf R D, Eaton P H, et al. Single event transient pulse widths in digital microcircuits [J]. IEEE Trans. Nucl. Sci., 2004, 51:3285-3290 被引量:1
  • 7Bessoy D, Velazco R. Design of SEU-hardened CMOS memory cells: the HIT cell [C]. Proceeding 1993 RADECS Conference, 1993:563-570 被引量:1
  • 8Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology [J]. IEEE Trans. Nucl. Sci, 1996, 43(6): 2874-2878 被引量:1
  • 9Bhuva B L, Black J D, Massengill L W. RHBD techniques for mitigating effects of single-event hits using guardgates[J]. IEEE Trans. Nucl. Sci, 2005, 52(6): 2531-2535 被引量:1

共引文献11

同被引文献17

  • 1周恒,李磊.一种加固SRAM单元DDICE及外围电路设计[J].微电子学与计算机,2015,32(5):68-72. 被引量:3
  • 2宋哲,王莉,陆剑侠,许仲德.SEU的二维数值模拟[J].微处理机,2005,26(1):37-39. 被引量:1
  • 3李海霞,李卫民,谭建平,陆时进.一种低功耗抗辐照加固256kb SRAM的设计[J].微电子学与计算机,2007,24(7):142-145. 被引量:9
  • 4Dodd P E, Massengill L W, Mavis D G, et al. Soft Error Rate Mitigation Techniques for Modem Micro- circuits[C]//Proc, of the 40th International Reliability Symposium. [S. 1.]: IEEE Press, 2002: 216-225. 被引量:1
  • 5Balasubramanian A, Bhuva B L, Black J D. RHBD Tech- niques for Mitigating Effects of Single-event Hits Using Guard-gates[J]. IEEE Trans. on Nuclear Science, 2006, 52(6): 2531-2535. 被引量:1
  • 6Calin T, Nicolaidis M, Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology[J]. IEEE Trans. on Nuclear Science, 1996, 43(6): 2874-2878. 被引量:1
  • 7Naseer R, Draper J. DF-DICE: A Scalable Solution for Soft Error Tolerant Circuit Design[C]//Proc of ISCAS'06. [S. 1.]: IEEE Press, 2006. 被引量:1
  • 8Naseer R, Draper J. The DF-DICE Storage Element for Immunity to Soft Errors[C]//Proc. of Midwest Symposium on Circuit and Systems. Cincinnati, USA: [s. n.], 2005: 303-306. 被引量:1
  • 9Garg R, Nagpal C, Khatri S E A Fast, Analytical Estimator for the SEU-induced Pulse width in Combinational Designs[C]//Proc. of the 45th ACM/IEEE Design Automa- tion Conference. [S. 1.]: ACM Press, 2008. 被引量:1
  • 10李玉红,赵元富,岳素格,梁国朕,林任.0.18μm工艺下单粒子加固锁存器的设计与仿真[J].微电子学与计算机,2007,24(12):66-69. 被引量:10

引证文献2

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部