摘要
The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.
The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.
