摘要
针对传统的Smith-Waterman硬件算法加速器未保存回溯路径而无法回溯的问题,通过将计算路径存入外存,在FPGA平台上基于脉动阵列实现了带回溯的Smith-Waterman算法加速器,详细阐述了算法加速器回溯设计中的关键技术以及算法加速器的系统结构。实验表明,与传统的解决方案相比,带回溯的算法加速器最高可获得161倍加速比,能够有效提高带回溯的Smith-Waterman算法执行效率。
The Smith-Waterman algorithm accelerator with backtracking, which has not been implemented in hardware before, is designed and implemented on FPGA platform with systolic array by storing the path data into DRAM. The key techniques of backtracking design and the architecture of algorithm accelerator are discussed in detail. Compared with the conventional scheme, the FPGA-based accelerator with backtracking is more effective, with the acceleration reaching 161.
出处
《国防科技大学学报》
EI
CAS
CSCD
北大核心
2009年第5期29-32,共4页
Journal of National University of Defense Technology
基金
教育部"高性能微处理器技术"创新团队资助项目(IRT0614)
