摘要
高压栅极驱动集成电路的实现中都设计有一定的开关噪声耐量,然而,由于结构上不是完全电隔离的,对噪声自然敏感,用于驱动感性负载时,开关换流期在高端浮动地上产生的过负压会使芯片闭锁,导致芯片高端驱动输出失常,甚至电路毁坏,就过负压产生原因、闭锁机理及在驱动集成电路的高端浮动地与桥输出之间加入电阻网络等电路级抑制措施进行了详细分析和介绍。
High-voltage gate- drive IC is designed with certain immunity against switching noise. However, the chip is sensitive to noise since it is not a complete galvanic isolation structure. With inductive load, an excessive negative voltage presented at the source of high - side switching device during commutation may cause the chip latch - up, which results in false operation or total circuit failure. The relationships between voltage undershoot and the latch - up mechanism are introduced in detail. Many means are analysed about to how to avoid the latch - up failure in circuit application level.
出处
《现代电子技术》
2009年第21期182-185,共4页
Modern Electronics Technique
