摘要
提出了一种基于AMBA总线系统的JPEG编码器的设计方案。通过总体架构方案和各个子模块的优化设计,在编码器的整体和局部两个层面提高了编码速率。通过仿真测试和FPAG验证,所设计的JPEG编码器在实际AMBA总线系统中正常工作,整体使用效率在70%以上,其核心部分(8*8的编码单元)的流水编码速率达到1像素/周期,完全可以满足数码相机等对图像进行实时编码的系统的需求。
This paper advances a design scheme of JPEG encoder based on AMBA system. Encoding speed is enhanced both on global and partial levels through the optimization design of system architecture and submodules. According to simulation test and FPGA verification, the JPEG encoder, which entire usage efficiency is beyond 70% and core part （8 ＊ 8 encode unit） pipeline encoding speed is up to 1 pixel per cycle, could work correctly in actual AMBA system, and fully meet the demands of real-time encoding applications such as digital cameras.
出处
《信息技术》
2009年第10期6-9,共4页
Information Technology
基金
上海-应用材料研究与发展基金(08700740700)
