摘要
分析了准循环低密度奇偶校验码生成矩阵的结构特点,讨论了硬件可实现的三种常见编码器结构,提出了一种混合结构的FPGA实现方法。通过利用循环矩阵的结构特性,增加少量硬件开销,就可以实现编码器高速编码,满足高速通信需求,吞吐量达1.36Gb/s。
Structural characteristics of QC-LDPC code generation matrix were analyzed, and three popular strut tures for hardware encoder were discussed. A mix-architecture was proposed for implementation of encoder in FP GA. In this design, high speed encoding with a throughput up to 1.36 Gb/s could be achieved by taking advantages of circulate matrix and adding some hardware resource, to satisfy the demand of high-speed communications.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第3期398-401,405,共5页
Microelectronics
基金
国家"973"计划基金资助项目(2009CB613306)
