摘要
本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法。采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器。基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试。该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率。
An encoder/decoder for the low density parity codes （LDPC） with FPGA techniques is implemented in this paper. An LDPC encoder is designed based on the Q-matrix construction method. The resulting encoder has the linear complexity with code block length. Based on soft-decision algorithm, a parallel decoder of LDPC code （rate 1/2, block length 40 bits） is realized. The whole design is verified through computer simulations. This decoder has the advantage of linear complexity with block length. It can be realized more easily and support higher throughput than Turbo code.
出处
《电路与系统学报》
CSCD
北大核心
2009年第5期60-65,共6页
Journal of Circuits and Systems
