摘要
在我国的数字电视广播地面传输标准DMB-T中,使用了准循环非规则LDPC码作为前向纠错编码。针对此标准中LDPC码的特点,采用修正最小和译码算法,设计了一种半并行结构实时译码器,可实现DMB-T中三种不同码率下的LDPC译码,并有效地实现了硬件结构复用。与其他设计方案相比较,减少了RAM块的数量一半以上,全局布线难度也大大降低。整个设计在StratixⅡ FPGA上进行了综合验证。当译码迭代次数为20次时,系统吞吐量可达100Mb/s以上。
In chinese national standard for Digital Multimedia Terrestrial Broadcasting（DMB-T）,QC irregular LDPC code is used as forward error correction coding.ln this paper, according to LDPC distribution property of DMB-T,based on modified Mini-SPA algorithm,a semi-parallel real-time LDPC decoder is presented.Hardware structure is specially optimized for 3 different code rates.Compared with others scheme,RAM block number can be decreased by half, so that global routing is simplified greatly.Whole design is synthesized on Stratix Ⅱ FPGA.When performing maxmum 20 iterations,decoder throughout can achieve data rate up to 100Mb/s.
出处
《计算机工程与应用》
CSCD
北大核心
2009年第11期77-81,共5页
Computer Engineering and Applications
