摘要
介绍了Dalsa公司的33M像素大面阵CCD的内部结构,着重分析了该款CCD的驱动时序。针对大面阵CCD图像传感器帧频较低的缺点,设计了基于现场可编程逻辑门阵列的驱动电路。改进了CCD芯片的偏置电压电路,提出了4路同时输出以提高帧频的电路设计方法,最高帧频可达2.7帧/s,相比单端输出时的0.7帧/s提高了约4倍。选用FPGA作为核心器件,使用VHDL语言设计驱动时序,在ISE和Modelsim环境下对所设计的驱动时序发生器进行仿真实验。实验结果表明,所设计的驱动电路能够满足大面阵CCD高帧频应用。
The inner structure of an array CCD device with 33M pixels made by Dasal corporation is introduced, and the driving schedule is analyzed in detail. Since the disadvantage of high sensitivity CCD which has lower frame rate, a design method of the full frame CCD drivers based on FPGA is put forward. To increase the frame rate by getting four outputs at the same time, the bias voltage circuit is improved. The frame rate reaches 2.7 f/s, effectively increased by about 4 times, compared with 0.7 f/s with single output. The system takes Field Programmable Gate Array （FPGA） as the key device and driving schedule generator has been described with VHDL. The designed generator has successfully fulfilled system simulation with ISE and Modelsim. It is proved that the driving system can meet the demand of the CCD in high frame rate application.
出处
《液晶与显示》
CAS
CSCD
北大核心
2009年第5期735-739,共5页
Chinese Journal of Liquid Crystals and Displays
关键词
面阵CCD
驱动电路
高帧频
FPGA
仿真
array CCD
driving circuit
high frame rate
field programmable gate array
simulation
