摘要
针对符合IEEE 802.11的MAC协议的芯片设计,介绍一种新的验证方案。该方案以功能覆盖率为驱动,使用约束随机的激励完成验证,大大降低了传统验证过程中对验证者个人经验的依赖,同时为验证的完备性提供了有效的度量手段。该方案使用Sysytem Verilog语言实现,根据VMM验证思想,搭建了一个层次化的逻辑验证环境。与传统的验证环境相比,该方案中的验证环境在验证自动化、组件重用等方面有突出的改进。实践证明,新的验证方案能够充分保证验证的完备性,同时能有效地提高验证效率,缩短验证周期。
Aiming at a design compatible with IEEE 802.11 MAC protocol,a new logic verification method is introduced.This new method is to build a coverage-driven,constrained random layered testbench using object oriented programming.It can reduce the relying on experiences of verification engineers.Meanwhile,it offers a very good measurement of verification completeness.A hierarchical testbench is developed based on SystemVerilog language and VMM.Compared to traditional verification environment,this new one has greatly improved in verification automation and reuse. It＇s proved in reality that this new method has greatly reduced verification time.
出处
《现代电子技术》
2009年第18期13-16,共4页
Modern Electronics Technique
