摘要
传统的验证平台编写复杂,且难以在不同设计之间重用。采用SystemVerilog支持的VMM验证方法学,并结合带约束的随机验证和覆盖率驱动的验证技术,构建可重用验证平台,完成对UART模块的验证。与直接测试方法相比,该验证平台不仅能够有效提高验证效率,而且在模块级和系统级验证过程中,能够重用该验证平台或验证组件。
It is complex to construct traditional test-bench,and difficult to reuse it among different designs.Constructing a layered and reusable test-bench by using the VMM methodology based on SystemVerilog language and adopting the random-constrained and coverage-driven verification technology to accomplish the verification of UART module.Comparing with the directed test,the proposed test-bench not only can make verification efficiently,but also can reuse the components in the process of module verification and system verification.
出处
《现代电子技术》
2011年第8期127-129,132,共4页
Modern Electronics Technique
