摘要
为提高高速通信系统的数据传输带宽,设计了一种基于FPGA、采用8b/10b编/解码、可应用于芯片与芯片或背板与背板之间通信的通用高速申行互连传输协议。介绍了点对点传输、全双工通信的协议体系结构,论述了协议物理层中数据传输时的串/并数据转换方法和帧同步机制,给出了协议链路层中循环冗余校验码算法、扰码/解扰模块、数据封装格式以及链路层控制器的设计。实验结果表明,系统设计的16bit位宽数据经8b/10b编码后,串行速率达到了1.25Gbps。
To improve the data transmission bandwidth of the high--speed communication system, in this paper, a general high--speed serial interconnection protocol based on FPGA and 8b/10b was designed, applying the communication between the chips or the backboards. Firstly, the protocol topology structure was introduced, adopting the spot to spot transmission and full-duplex communication. And then, in the protocol＇ s physics layer, the conversion technique of the serial/parallel data and the frame in-phase mechanism were discussed. Fi nally, in the protocol＇ s link layer, the designing of the arithmetic of cyclical redundancy check, scrambler and descrambler, the encapsulation format of data and link layer controller were presented. The experiment shows that the serial speed reaches to 1.25Gbps, after the 16hit wide data coded by 8b/10b.
出处
《计算机测量与控制》
CSCD
北大核心
2009年第9期1826-1827,1830,共3页
Computer Measurement &Control
