摘要
依据CSA算法,对CAM卡中的解扰模块进行设计。采用verilog HDL语言设计。利用modelsim对其设计结果进行仿真验证。并在Xilinx上实现FPGA综合。设计结果可靠有效。具有很高的实用价值和市场价值。
In this paper,according to the CSA arithmetic,we put forward a design and implementation of descrambler in CSA card.The whole design is described with verilog HDL,verified with modelsim and synthesized on the FPGA of Xilinx.The result of design proves correct and effective.The design has highly useful value as well as market value.
出处
《计算机与数字工程》
2008年第1期120-122,127,共4页
Computer & Digital Engineering
基金
模拟集成电路国家重点实验室基金(项目编号:9140C0905040706)资助
