摘要
文中基于FPGA技术设计了一个16阶FIR数字低通滤波器。采用分布式算法作为滤波器的硬件实现算法。通过将FIR滤波器的乘加运算转化为查找表,极大提高了FIR滤波器的速度。在程序设计中采用了层次化、模块化的设计思想,将整个滤波器划分为多个功能模块。仿真结果表明:文中设计的滤波器硬件规模较小。同时只要将查找表进行相应的改动,就能分别实现低通、高通、带通FIR滤波器,体现了设计的灵活性。
A 16-order finite impulse response（FIR） digital low-pass filter is designed on the basis of FPGAtechnology with distributed algorithm. By replacing MAC units with lookup table the speed of the FIR filter is greatly improved. With the design thought of modularization and level diversification, the whole design is divided into several function modules. Simulation result shows that the hardware is small-scaled and flexible. The low-pass, high pass, or band-pass FIR filter could be easily realized by accordingly modifying the lookup table.
出处
《通信技术》
2009年第9期3-6,共4页
Communications Technology
基金
国家自然科学青年基金项目(60802025)
北京市教委科学技术面上项目(km200710772001)
