摘要
为了实现高速串行通讯,设计了基于FPGA的RS485总线的通讯接口,FPGA与DSP之间采用双FIFO进行数据缓存,并且通过DSP总线与DSP进行数据交换;开发了以FPGA和DSP为核心的原理图与印制电路板,使用VHDL语言开发了HDLC通讯协议的控制时序。实验结果表明:系统的持续存储速度可以达到1Mbit/s,工作稳定可靠,没有丢帧、串帧等丢失数据现象。
In order to implement high speed serial communication, a communication interface of RS485 bus is designed based on FPGA. Between FPGA and DSP, there are two FIFO cache, the communication data are exchanged by DSP data bus. The PCB card which is centered by the DSP and FPGA, and programs the HDLC protocol with VHDL are designed. Experiment results show that the communication speed can reach 1 Mbit/s, and the system works stable without error.
出处
《电子器件》
CAS
2009年第3期707-710,共4页
Chinese Journal of Electron Devices
