摘要
比较器可以比较一个模拟信号和参考信号,并且输出比较得到的二进制信号。为了设计一个高速度、高精度的比较器,采用预放大锁存比较电路结构,并加以改进。在Cadence环境下基于CSMC 0.5μm CMOS工艺完成比较器的电路设计、版图设计和版图验证。仿真得到比较器的增益为85.588 4 dB,带宽为60.546 7 MHz,上升延时为5.723 74 ns,下降延时为5.429 17 ns,输入失调电压为640.17μV。它适用于高速A/D等领域的应用。
A comparator can compare an analog signal with a referential signal and get a binary system signal. The preamplified and locked circuit is used and improved for designing a high precision and high speed comparator. Then,the design of circuit and layout and the validation of layout are completed under Cadence based on CSMC 0. 5μm CMOS process. After simulation, the gain of the design is 85. 588 4 dB,the frequency bandwidth is 94.8 MHz,the rise delay time is 5. 7237 4 ns,the down delay time is 5.429 17 ns and the offset voltage of import is 640. 17μV. It is fit for high speed system s.uch as A/D.
出处
《现代电子技术》
2009年第14期7-9,共3页
Modern Electronics Technique
基金
贵州省科技攻关资助项目:高精度低漂移集成电压基准源研制(GY[2008]3033)
关键词
比较器
模拟信号
二进制信号
高速高精度
comparator
analog signal
binary signal
high precision and high speed
