摘要
介绍了一个高速１２位分区式Ａ／Ｄ转换器的设计。电路采用“３位＋３位＋８位”的三级分区式结构。其中的８位ＡＤＣ为折叠插入式ＡＤＣ，误差校正采用模拟校正、数字编码形式。采用２μｍＢｉＣＭＯＳ设计规则设计的电路，经ＰＳＰＩＣＥ仿真，在±５Ｖ电源下，采样频率高达３ＭＨｚ。
A monolithic high speed 12bit subranging A/D converter for CCD imaging has been developed. Characteristics of the circuit and its architecture are described in detail. A “3bit+3bit+8bit” threestage subranging configuration is adopted, where the 8bit circuit is a folding and interpolating ADC. Analog correction with digital coding is used for error correction. A builtin clock generator provides strobe clock signals for 3 subranging conversion subsystems. SPICE simulation of the device indicates that a sampling frequency up to 3 MHz at ±5 V supply is achievable.
出处
《微电子学》
CAS
CSCD
北大核心
1998年第4期254-259,共6页
Microelectronics
关键词
模拟集成电路
A/D转换器
数字信号处理
Analog IC,Analogtodigital converter, Digital signal processing
