摘要
三态传输门正边沿主从寄存器,在单时钟系统中时钟重叠期间,会导致在非时钟上升沿期间采样,以及输出在负边沿发生变化.针对这一情况介绍了一种改进的三态门正边沿主从寄存器,避免上述的竞争情况,满足控制精度较高的场合使用,并在1stSilicon0.25μm2.5V电压工艺下给出的瞬态仿真与版图实现.
The Tri-State-TG,positive edge sensitive,master-slave,register,during the clock overlap period of single-clock system,will lead to sample in the non-clock positive edge and the data output will change in the negative edge.This article is based on this model to design an advanced Tri-State-TG,positive edge sensitive,master-slave register,avoiding racing and fulfilling the high-precision control situation.The author presents the simulation and layout in the 1st-Silicon 0.25μm 2.5V processing standard.
出处
《微电子学与计算机》
CSCD
北大核心
2009年第5期231-234,共4页
Microelectronics & Computer
