摘要
对于流水线型的超大规模微处理器,通常采用多端口的寄存器堆暂存中间数据,这些读写操作势必增加寄存器堆的芯片面积和功耗。因此提出一种基于double-pumped的采样时钟,在一个系统时钟周期内用一根复用地址线顺序完成读写操作,从而大大减少芯片面积,并降低系统功耗。采用1.2V,0.13!m的CMOS工艺进行仿真,结果显示该2读1写寄存器堆在1GHz工作频率下,其数据读取时间仅为546ps。
A multi-ported register file is often required by the superscalar microprocessor to handle multiple simultaneous loads and stores, which cause large increase in area and power consumption. In this paper, it proposed a double- pumped clock to achieve same cycle reads and writes with a single sharing line, which can largely help to reduce the power consumption and layout area. A 2-Read 1-Write register file proves to work at 1GHz with 546ps access time in a 1.2V, 0A3μm CMOS technology.
出处
《微电子学与计算机》
CSCD
北大核心
2007年第11期89-91,94,共4页
Microelectronics & Computer
基金
上海科技部国际合作基金项目(055207041)
关键词
寄存器堆
复用
地址线
功耗
register file
sharing
word line
power consumption
