摘要
传统SOI DTMOS器件固有的较大体电阻和体电容严重影响电路的速度特性,这也是阻碍SOI DTMOS器件应用于大规模集成电路的最主要原因之一。有人提出通过增大硅膜厚度的方法减小器件体电阻,但随之而来的寄生体电容的增大严重退化了器件特性。为了解决这个问题,提出了一种SOI DTMOS新结构,该器件可以分别优化结深和硅膜的厚度,从而获得较小的寄生电容和体电阻。同时,考虑到沟道宽度对体电阻的影响,将该结构进一步优化,形成侧向栅-体连接的器件结构。ISE-TCAD器件模拟结果表明,较之传统SOI DTMOS器件,该结构的本征延时和电路延时具有明显优势。
The performance of partially depleted silicon-on insulator （PDSOI） dynamic threshold MOSFET（DTMOS） devices is degraded by body capacitance and body resistance. The large body capacitance and RC delay in charging the body are serious issues in implementing SOI DTMOS. To solve this problem, a novel SOI DTMOSFET structure （drain and source on local insulator structure） was proposed and optimized. To improve the dependence of RbCb on the value of W, a method was proposed based on the novel SOI DTMOSFET structure. From ISE simulation, the improvement in delay, obtained by shallow depth source/drain junctions and by optimizing Tsi, was very significant, compared with conventional PDSOI-DTMOS.
出处
《微电子学》
CAS
CSCD
北大核心
2009年第2期280-284,共5页
Microelectronics
基金
国家基础研究重大项目基金资助(206CB3027-01)
关键词
绝缘体上硅
动态阈值场效应管
体电容
体电阻
Silicon-on-insulator （SOD
Dynamic threshold MOSFET （DTMOS）
Body capacitance
Body resistance
