摘要
提出了一种节能并可升级的异步FIFO的FPGA实现。此系统结构利用FPGA内自身的资源控制时钟的暂停与恢复,实现了高能效、高工作频率的数据传输。该系统在Xilinx的VC4VSX55芯片中实现,实际可工作于高达100/153.6MHz的读/写时钟域。本文所提出的结构不依赖于现有的IP核,基于此结构易建立可升级的IP核。
A power-efficient and scalable asynchronous First In First Out （FIFO） using FPGA is presented in this paper. This architecture achieves high power efficiency and high work frequency by clock halting and restoring technology of embedded FPGA resources. The proposed system is demonstrated on platform of Xilinx VC4VSX55, which achieves 100/153.6 MHz operation across reading and writing clock domain. Its performance and stability has been tested. The structure proposed does not relay on the recent IP core. It is suitable for establishing scalable IP core.
出处
《电子技术应用》
北大核心
2009年第4期66-69,共4页
Application of Electronic Technique
