摘要
位同步环是实现全数字接收机中定时恢复的关键技术,本文设计采用早门、迟门积分对比得到位时钟误差的鉴别方式,对位时钟误差的鉴别结果进行积累滤波,滤波结果实时调整数控振荡器,调节本地位时钟跟踪输入位时钟。文中给出了该位同步环的工作原理、实现框图、资源分析,仿真结果验证了方法的有效性。整个位同步环路基于FPGA实现,易于编程、改进和移植。
： Bit synchronization is one of key technologies to achieve all-digital receiver timing recovery. This design gets bit clock error by comparing integration between early-door and late-door, then the result of discrimination is accumulated to filter noise. DCO is adjusted by the filter results and then regulate the status clock to track the input clock. In this paper, working principle, realization diagram and resource analysis are given. Then simulation results show the effectiveness of the method. The entire bit synchronization loop based on FPGA implementation is easy to program, improve and transplant.
出处
《微计算机信息》
2009年第8期178-179,272,共3页
Control & Automation
关键词
全数字接收机
位同步
早门迟门
FPGA
all digital receiver
bit synchronization
early- late gate
FPGA
