摘要
本文采用维数缩减技术(DRT)提取了多层介质中通孔结构的准静态电容参数。由于该方法充分利用了集成电路结构分层性的特点,从而可以很方便地处理任意的介质层数和结构参数,而仅需很少的计算时间和内存.文中的计算结果与Ansoft软件结果符合较好。
An efficient method to calculate the quasi-static capacitance of the via hole structure embedded in a multilayered dielectric media named Dimension Reduction Technique(DRT) is presented. Since the method takes full advantage of the characteristics of the stratified structure in integrated circuit, it can easily deal with the varied numbers of the dielectric layers as well as the varied structure parameters while only need little CPU time and memory space. The numerical results given in this paper are in good agreement with those of Ansoft's software.
关键词
参数提取
准静态电容
数字集成电路
Parameter extraction, Quasi-static capacitance, 3D interconnect, Via hole, Dimension Reduction Technique(DRT)
