摘要
本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性．对于底层的电路设计，应将互连看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件．基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形全部考虑在内．数值结果表明，这种逻辑模型具有较高的精度和效率．此外，针对逻辑模型的提取，本文还提出了计算多组输人信号瞬态响应的快速算法所应具有的特性．
A novel idea is presented in this paper for the first time. The equivalent model of the interconnects in the VLSI circuits should be hierarchical. For the low level circuit designing,the interconnects should be treated as multiport networks with distributed parameters;for the high level module designing,they should be treated as logic elements. Based upon this idea,a table logic model of the interconnects in VLSI circuits is presented. Three major negative effects, namely,crosstalk,signal distortion and delay,'are all considered in this model. Numerical results show that this model is accurate and efficient. Besides,features of the algorithms for the fast calculation of the transient responses to multiple input patterns are also proposed.
出处
《电子学报》
EI
CAS
CSCD
北大核心
1997年第2期39-44,28,共7页
Acta Electronica Sinica
关键词
互连
逻辑模型
VLSI
VLSI circuits,Interconnects,Logic model
