摘要
介绍了一种带宽150 kHz、16 bit的∑-Δ模数转换器中的降采样低通滤波器的设计和实现。系统采用Sharpened CIC(cascaded integrator-comb)和ISOP(interpolated second-order polynomials)频率补偿技术对通带的下降进行补偿,最后级联三个半带滤波器输出。芯片采用SMIC 0.18μmCMOS工艺实现,系统仿真和芯片测试结果表明,性能满足设计指标要求。与传统音频领域的∑-ΔADC应用相比,该设计在很大程度上拓展了处理带宽,提高了处理精度,并且便于集成在SOC芯片中,主要应用于医疗仪器、移动通信、过程控制和PDA(personal digital assistants)等领域。
A decimation low pass filter was described for a 16 bit ∑-△ analog-to-digital converter （ADC） capable of converting input frequencies up to 150 kHz. This filter compensated the drop of passband with the technique of Sharpened CIC （cascaded integrator-comb） and ISOP （interpolated second-order polynomials）. It cascaded three halfband filters in the end for output. The filter was implemented in SMIC 0.18 μm CMOS technology. The system simulation result and IC test result prove that its performance meets the design specification. Comparing with the traditional audio ∑-△ ADC application, this design expands the processing bandwidth and improves the precision. It can be easily integrated in the SOC chips, it is mainly used in the medical instruments, mobile communication, process control and PDA （personal digital assistants） etc.
出处
《半导体技术》
CAS
CSCD
北大核心
2008年第12期1133-1137,共5页
Semiconductor Technology
