摘要
为了抑制小数分频锁相环产生的量化噪声,提高锁相环的性能,设计并实现了一种基于FPGA的MASH1-1-1结构∑-Δ调制器。根据小数分频锁相环的原理,分析了量化噪声产生的原因,详细介绍了在小数频率合成器中应用∑-Δ调制器进行噪声整形的基本原理及在FPGA中的实现方法。仿真结果表明,经过MASH1-1-1三阶∑-Δ调制器整形后的量化噪声大部分被推到频率高端,只有小部分噪声能量还留在环路带宽内,有效地提高了锁相环的性能。
In order to suppress quantization noise occurring in fractional-N and improve the performance of PLL,a MASH1-1-1 Architecture Σ-Δ modulator was designed based on FPGA.According to the principle of fractional-N PLL,the reasons leading to quantization noise were analyzed.The principle of ∑-Δ modulator applied to the Fractional-N Frequency Synthesis and its realization in FPGA was introduced in detail.Simulation results show that most noise is transferred to high frequency region by the third-order MASH1-1-1 Σ-Δ modulator and only little noise energy remains in the loop bandwidth,thus the performance of PLL is effectively improved.
出处
《中国测试》
CAS
2010年第5期76-78,共3页
China Measurement & Test
