摘要
分组密码算法是一种常用的密码技术。其加密速度非常快,在数据加密领域仍广泛使用。目前,分组密码的重点研究方向包括新型分组密码的研究,分组密码的实现研究,分组密码的各个组件的研究等等。本文从AES的5个候选算法中提炼出7大分组算法模块,分别用VHDL和Verilog实现,并对资源占用情况加以分析比较。然后选取分组算法的典型代表AES,用两种语言实现并对资源占用情况和实现速率加以比较。结果表明:对于小型分组算法模块,VHDL和Verilog的实现在占用逻辑单元方面基本上没有什么差别;对较为复杂的模块和AES算法,Verilog的实现会比VHDL的实现占用较少的资源,但速度要慢些。
Block cipher is a kind of cipher structure. For its very fast encryption speed, the block cipher is still widely used in data encryption field. Nowadays, the main studying direction for block cipher focuses on the study of new types, the study of block cipher realization, the study of block cipher components and so on. In this paper, seven block cipher modules from the five AES candidates are selected, then realized with VHDL and Yerilog. The consumption of resources between the two are analyzed and compared. Then the AES, a typical block cipher is selected and realized with VHDL and Verilog. The results are ：l）for the small block cipher modules, there is little difference on the consumption of resources; 2）for complex modules and AES, the realization with Yerilog consumes less resources than the realization with VHDL, but the speed is slower.
出处
《通信技术》
2008年第12期353-354,357,共3页
Communications Technology
基金
北京电子科技学院重点实验室资助项目
